The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-access port. This flexibility enables the minimization of the overall access time (OAT), and a number of techniques have been proposed in the literature to achieve this goal. However, the OAT is still high for instruments that require a large amount of test data if this data is shifted through the scan chain serially. In order to further reduce the OAT, we present an efficient test-scheduling method that exploits broadcast and hardware parallelism for instrument access. A broadcast scheduling method is synergistically combined with three parallel IJTAG designs. We show that under different cost criteria, we can select the most efficient parallel IJTAG design such that the equivalent access time (EAT) is minimized. In addition, an interconnect fabric design and an integer-linear-programming method is used to balance the lengths of multiple scan chains. Two industry chip designs and three IJTAG benchmarks are used to evaluate the effectiveness of the proposed method.

中文翻译：

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使用数据广播和硬件并行的 IJTAG 网络访问时间最小化

IEEE 标准 1687 有助于通过 JTAG 测试访问端口灵活访问片上仪器。这种灵活性使总访问时间 (OAT) 最小化，并且文献中已经提出了许多技术来实现这一目标。然而，对于需要大量测试数据的仪器，如果这些数据在扫描链中串行移动，OAT 仍然很高。为了进一步减少 OAT，我们提出了一种有效的测试调度方法，该方法利用广播和硬件并行性进行仪器访问。一种广播调度方法与三个并行的 IJTAG 设计相结合。我们表明，在不同的成本标准下，我们可以选择最有效的并行 IJTAG 设计，以使等效访问时间 (EAT) 最小化。此外，互连结构设计和整数线性规划方法用于平衡多个扫描链的长度。使用两个工业芯片设计和三个 IJTAG 基准来评估所提出方法的有效性。