We propose three orthogonal techniques to secure Register-Transfer-Level (RTL) Intellectual Property (IP). In the first technique, the key-based RTL obfuscation scheme is proposed at an early design phase during High-Level Synthesis (HLS). Given a control-dataflow graph, we identify operations on non-critical paths and leverage synthesis information during and after HLS to insert obfuscation logic. In the second approach, we propose a robust design lockout mechanism for a key-obfuscated RTL IP when an incorrect key is applied more than the allowed number of attempts. We embed comparators on obfuscation logic output to check if the applied key is correct or not and a finite-state machine checker to enforce design lockout. Once locked out, only an authorized user (designer) can unlock the locked IP. In the third technique, we design four variants of the obfuscating module to camouflage the RTL design. We analyze the security properties of obfuscation, design lockout, and camouflaging. We demonstrate the feasibility on four datapath-intensive IPs and one crypto core for 32-, 64-, and 128-bit key lengths under three design corners (best, typical, and worst) with reasonable area, power, and delay overheads on both ASIC and FPGA platforms.

中文翻译：

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具有设计锁定和伪装的密钥混淆 RTL IP 的高级综合

我们提出了三种正交技术来保护寄存器传输级 (RTL) 知识产权 (IP)。在第一种技术中，基于密钥的 RTL 混淆方案是在高级合成 (HLS) 期间的早期设计阶段提出的。给定一个控制数据流图，我们识别非关键路径上的操作，并在 HLS 期间和之后利用综合信息插入混淆逻辑。在第二种方法中，我们为密钥混淆的 RTL IP 提出了一种健壮的设计锁定机制，当错误密钥的应用次数超过允许的尝试次数时。我们在混淆逻辑输出上嵌入比较器以检查应用的密钥是否正确，并在有限状态机检查器中嵌入以强制设计锁定。一旦锁定，只有授权用户（设计者）才能解锁锁定的 IP。在第三种技术中，我们设计了四种混淆模块的变体来伪装 RTL 设计。我们分析了混淆、设计锁定和伪装的安全属性。我们在三个设计角（最佳、典型和最差）下展示了四个数据路径密集型 IP 和一个用于 32 位、64 位和 128 位密钥长度的加密内核的可行性，并且两者都具有合理的面积、功率和延迟开销ASIC 和 FPGA 平台。