A simulation study of the Off-State breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented. The proposed device is a modification of a bulk-LDMOS transistor with a single dummy gate and two different diffused layers in the drift region. It introduces two additional dummy gates in the drift region, apart from the gate and extended drain electrode in the conventional device. The dummy gates need to be optimally biased to maximise the breakdown (V_BR) and snapback voltages. 1D model modifying the 2D Poisson's equation has been proposed to analyse the 2D phenomena arising due to the perpendicular electric field originating from the dummy gate and extended-drain voltages and optimize the two dummy-gates bias. This approach provides an analytical solution for the Off-State V_BR under the depletion condition. The model is verified with the TCAD simulations. The simulation results provide an insight into the electric field, potential distributions, and carrier concentrations in the drift region that characterizes the device performance. The impact ionization and current density contours are also included. It is found that the introduction of the two dummy gates enhances the maximum achievable V_BR while it eliminates the need to have two different diffused regions that necessitate additional masks. Also, the proposed device has an intrinsic structural advantage of the reduced gate to drain capacitance due to the shielding effect of dummy gates. As the performance of the proposed device is controlled externally by the applied dummy gate voltage, the V_BR is user programmable as per the requirement in electrostatic discharge (ESD) protection circuits for a sub-100 V application.

提出了双虚拟栅SOI-LDMOS晶体管的截止状态击穿特性的仿真研究。拟议的器件是体LDMOS晶体管的一种改进，在漂移区内具有单个虚设栅极和两个不同的扩散层。除了传统器件中的栅电极和扩展的漏电极，它还在漂移区引入了两个附加的伪栅。虚拟栅极需要最佳偏置，以使击穿电压（V _BR）和骤回电压最大化。提出了修改2D泊松方程的1D模型，以分析由于虚拟栅极和扩展漏极电压引起的垂直电场而产生的2D现象，并优化两个虚拟栅极偏置。这种方法为关闭状态提供了一种分析解决方案V _BR在耗尽条件下。该模型已通过TCAD仿真进行了验证。仿真结果提供了对电场，电势分布和漂移区域中载流子浓度的洞察力，这些区域表征了器件的性能。冲击电离和电流密度等值线也包括在内。发现两个伪栅极的引入增强了最大可实现的V _BR同时消除了需要使用两个额外的掩模的两个不同扩散区域的需要。而且，由于伪栅极的屏蔽效应，所提出的器件具有减少栅极到漏极电容的固有结构优势。由于拟议器件的性能由施加的虚设栅极电压从外部控制，因此V _BR可根据低于100 V应用的静电放电（ESD）保护电路的要求进行用户编程。