To go through the phenomenon at nanoscale regimes, circuits using the CNTFETbased on Ternary Logic have been explored due to their constantly increasing application in high-speed low power designs. In this paper, 4-Trit Ternary Adder-Subtractor (TAS) using Complementary metal-oxide-semiconductor (CMOS) and Carbon Nanotube Field-Effect Transistor (CNFET) is proposed, which demonstrates the ternary addition and subtraction with a single circuit. The design style is based on conventional static CMOS implementation. The Fundamental ternary logic units are connected to achieve the required design. Therefore, prominence is given to the optimization of these fundamental units. The implementation and simulation are analyzed and validated using Hailey Simulation Program with Integrated Circuit (HSPICE) with PTM low power 32 nm metal gate / High-K / Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CMOS based design is compared with the CNTFET design in terms of key design factors, namely average delay, power consumption and power delay product(PDP). The simulation results reveal that CNTFET based 4-Trit Ternary Adder-Subtractor accomplishes better results in comparison with CMOS based 4-Trit Ternary Adder-Subtractor design. When compared with CMOS-based 4-Trit TAS, it is found that in CNTFET based 4-Trit TAS the average delay and power consumption is improved by approximately 82% and 71% respectively.

为了在纳米尺度上克服这种现象，由于基于三元逻辑的CNTFET在高速低功耗设计中的不断增加的应用，已经探索了这些电路。本文提出了一种采用互补金属氧化物半导体（CMOS）和碳纳米管场效应晶体管（CNFET）的四重三元加减法（TAS），以单电路演示三元加法和减法。设计风格基于常规的静态CMOS实现。连接基本三元逻辑单元以实现所需的设计。因此，突出这些基本单元的优化。使用带有集成电路的Hailey仿真程序（HSPICE）对实现和仿真进行了分析和验证，该程序具有用于CMOS的PTM低功耗32 nm金属栅极/高K /应变硅模型和用于CNTFET的32 nm Stanford模型。将基于CMOS的设计与CNTFET设计在关键设计因素（即平均延迟，功耗和功率延迟乘积（PDP））方面进行了比较。仿真结果表明，与基于CMOS的4位三进制加减法设计相比，基于CNTFET的4位三进制加减法实现了更好的结果。与基于CMOS的4-Trit TAS进行比较时，发现在基于CNTFET的4-Trit TAS中，平均延迟和功耗分别提高了约82％和71％。将基于CMOS的设计与CNTFET设计在关键设计因素（即平均延迟，功耗和功率延迟乘积（PDP））方面进行了比较。仿真结果表明，与基于CMOS的4位三进制加减法设计相比，基于CNTFET的4位三进制加减法实现了更好的结果。与基于CMOS的4-Trit TAS进行比较时，发现在基于CNTFET的4-Trit TAS中，平均延迟和功耗分别提高了约82％和71％。将基于CMOS的设计与CNTFET设计在关键设计因素（即平均延迟，功耗和功率延迟乘积（PDP））方面进行了比较。仿真结果表明，与基于CMOS的4位三进制加减法设计相比，基于CNTFET的4位三进制加减法实现了更好的结果。与基于CMOS的4-Trit TAS进行比较时，发现在基于CNTFET的4-Trit TAS中，平均延迟和功耗分别提高了约82％和71％。