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Wave-digital filter circuits for single-chip 4-D light field depth-based enhancement
Multidimensional Systems and Signal Processing ( IF 1.7 ) Pub Date : 2021-01-02 , DOI: 10.1007/s11045-020-00751-y
Sai K. Gullapalli , Chamira U. S. Edussooriya , Chamith Wijenayake , Donald G. Dansereau , Len T. Bruton , Arjuna Madanayake

In four-dimensional (4-D) light field (LF) processing, 4-D linear shift-invariant filters having hyperplanar passbands are used for depth-based scene enhancement. In this paper, two low-sensitivity and low-complexity field programmable gate array (FPGA)-based digital hardware architectures for 4-D hyperplanar filters are proposed for on-chip real-time processing of LFs. Both 4-D filters are designed exploiting resonant properties of multi-dimensional passive prototype networks, and are realized as wave digital filters (WDFs). The two 4-D WDF realizations are implemented as raster-scanned processing architectures on a Xilinx Virtex 6 Sx35 FPGA with a real-time clock speed of up to 33 MHz. This corresponds to a real-time throughout of 16.8 LFs/s for an LF of size $$11 \times 11 \times 128 \times 128$$ 11 × 11 × 128 × 128 .

中文翻译:

用于单芯片 4-D 光场深度增强的波数滤波电路

在四维 (4-D) 光场 (LF) 处理中,具有超平面通带的 4-D 线性位移不变滤波器用于基于深度的场景增强。在本文中,提出了两种基于低灵敏度和低复杂度的现场可编程门阵列 (FPGA) 数字硬件架构,用于 4-D 超平面滤波器,用于 LF 的片上实时处理。两种 4-D 滤波器均利用多维无源原型网络的谐振特性进行设计,并作为波形数字滤波器 (WDF) 实现。这两个 4-D WDF 实现在 Xilinx Virtex 6 Sx35 FPGA 上实现为光栅扫描处理架构,实时时钟速度高达 33 MHz。对于大小为 $$11 \times 11 \times 128 \times 128$$ 11 × 11 × 128 × 128 的 LF,这对应于 16.8 LFs/s 的实时吞吐量。
更新日期:2021-01-02
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