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Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods
Microsystem Technologies ( IF 1.6 ) Pub Date : 2021-01-03 , DOI: 10.1007/s00542-020-05118-8
Pranati Ghoshal , Chanchal Dey , Sunit Kumar Sen

An energy and area efficient switching scheme for a 4-bit charge redistribution switch capacitor (SC) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. Single and two step reset energies are also considered for calculations of energy efficiencies. The designed architecture consumes zero energy in the first and third comparison cycles where energy consumptions are relatively high, leading to high energy efficiency. It is seen that switching energy, without reset, is as high as 99%. With reset energy taken into consideration, energy savings become 98.44% and 98.4% for single and two step reset methods respectively. Thus the method becomes one of the most energy efficient switching schemes recently presented by different researchers. The scheme also achieves a 75% reduction in unit capacitance requirements over the conventional method. It is also seen that both INL and DNL of the proposed method are better than several other established methods.



中文翻译:

使用单步复位和两步复位方法实现超低功耗和面积高效的SC SAR ADC架构

提出了一种用于4位电荷重新分配开关电容器(SC)逐次逼近寄存器(SAR)模数转换器(ADC)的节能高效的开关方案。计算能量效率时还考虑了单步复位能量和两步复位能量。在能量消耗相对较高的第一个和第三个比较周期中,设计的架构消耗的能量为零,从而实现了高能效。可以看出,未经复位的开关能量高达99%。考虑到复位能量,对于单步复位方法和两步复位方法,节能分别为98.44%和98.4%。因此,该方法成为不同研究人员最近提出的最节能的切换方案之一。与传统方法相比,该方案还可将单位电容要求降低75%。还可以看出,提出的方法的INL和DNL均优于其他几种已建立的方法。

更新日期:2021-01-03
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