High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process \(32\times 32\) CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD \((8192\times 4320)\) @ 78 fps.

高效视频编码（HEVC）是最新的视频编码标准，通过提供比其以前的标准H.264大约两倍的压缩效率，支持高分辨率视频。HEVC中的运动估计（ME）是计算量最大的块，因此，它成为编码器设计的瓶颈，同时在各种计算平台（例如通用和嵌入式处理器）上实现视频应用程序。因此，在现场可编程门阵列（FPGA）和专用集成电路（ASIC）平台上开发计算高效的体系结构是不可避免的。本文提出了一种用于UHD视频编码的快速混合搜索模式算法及其硬件架构。提出的Integer ME（IME）算法平均需要11。与HM参考软件中的默认“测试区域搜索”（TZS）算法相比，编码时间减少了19％，同时降低了PSNR的降低和比特率的提高。利用台积电90纳米技术库，在FPGA和ASIC平台中都实现了所建议的体系结构。它消耗了Virtex-7 FPGA的32-33％的资源，以及2784.4 K等效门数（按NAND计）和18 kB存储器。结果表明，该架构的最大频率为162 MHz，总功耗为463.4 mW。由于其处理过程，该架构提供的最大吞吐量为2.78 Gpixels / sec 它消耗了Virtex-7 FPGA的32-33％的资源，以及2784.4 K等效门数（按NAND计）和18 kB存储器。结果表明，所提出架构的最大频率为162 MHz，总功耗为463.4 mW。由于其处理过程，该架构提供的最大吞吐量为2.78 Gpixels / sec 它消耗了Virtex-7 FPGA的32-33％的资源，以及2784.4 K等效门数（按NAND计）和18 kB存储器。结果表明，该架构的最大频率为162 MHz，总功耗为463.4 mW。由于该过程，该架构提供了2.78 Gpixels / sec的最大吞吐量。与最新文献相比，\（32×32） CU的时钟周期要少得多（59.5）。此外，它支持8K UHD \（（8192 \ times 4320）\） @ 78 fps。