In order to suppress the spurious signal resulted from the reference leak and to decrease the oscillator jitter by using phase locked loop (PLL) loop band extension, a reference frequency multiplier that places a delay locked loop (DLL) in front of the PLL has been studied. However, a feedback circuit such as a DLL or an injection locked type voltage controlled oscillator must be used. In this paper, we propose a novel digital PLL capable of reference frequency multiplication without a feedback circuit. Simulink estimated the phase noise improved by − 17 dB at 1 MHz offset, and the spurious tones due to device variation reduced by − 12 dB with a dynamic element matching.

为了抑制参考泄漏引起的寄生信号并通过使用锁相环（PLL）环路带宽扩展来降低振荡器抖动，已经将在锁相环前面放置了延迟锁定环（DLL）的参考倍频器进行了设计。研究。但是，必须使用诸如DLL或注入锁定型压控振荡器之类的反馈电路。在本文中，我们提出了一种新型的数字PLL，该数字PLL无需参考电路即可进行参考倍频。Simulink估计，在1 MHz偏移处，相位噪声改善了− 17 dB，并且在动态元件匹配的情况下，由设备变化引起的杂音降低了− 12 dB。