In this work we study the epitaxial Si growth with Si₂H₆ for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D_it < 510¹¹ cm⁻² eV⁻¹. Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm₂O₃/HfO₂ gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 310¹¹ eV⁻¹ cm⁻² and a significant improvement in oxide trap density compared to GeO_x passivation.

在这项工作中，我们研究了用于CMOS器件中Ge表面钝化的Si ₂ H ₆的外延Si生长。Si盖层在标称温度为400 C的氢解吸受限条件下在Ge上生长。我们评估了界面态密度的工艺窗口，并表明对于D，在8到9个单层之间有最佳的Si盖层厚度_它<510 ¹¹ cm ^-2 eV ^-1。此外，我们讨论了硅盖生长时间和温度对界面态密度的强烈影响，这是由于硅厚度对这些生长参数的依赖性而引起的。此外，我们成功转移了TmSiO / Tm ₂ O ₃ / HfO ₂与具有GeO _x钝化相比，具有优化的Si-cap的从Si到Ge器件的栅堆叠工艺，界面态密度为310 ¹¹ eV ^-1 cm ^-2，并且氧化物陷阱密度得到了显着改善。