This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps.

中文翻译：

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基于降低的复杂度XOR树的IEEE 802.11n / ac / ax QC-LDPC码的多速率全并行LDPC编码器

本文针对IEEE 802.11n / ac / ax标准中指定的12种准循环（QC）-低密度奇偶校验（LDPC）（QC-LDPC）码，提出了一种基于两步编码算法的编码方法。所提出的方法共同考虑了特定集合的所有代码，而不是分别针对每个代码。所提出的算法通过逆矩阵执行乘法。所引入的编码方法大大降低了乘法的复杂性。它允许实施全并行体系结构，以在单个时钟周期内执行编码过程，对于任何受支持的代码，则可以在流水线实施中执行更多的编码过程。还提出了一种基于异或门树的相应VLSI编码架构。所提出的解决方案利用所涉及的矩阵的结构和特征，使用公共子表达式共享技术（CSST）来提取公共子表达式（CS）。之所以产生这种表达式，是因为本文确定了原始矩阵和相应逆的共同特征。在此介绍针对特定代码的创新子表达式提取过程。此外，通过该技术派生的说明性单时钟硬件编码器已集成到1 GHz的90纳米和45纳米技术中，分别占用125 KG和107 KGate，实现了高达1.62 Tbps的吞吐速率。在本文中确定。在此介绍针对特定代码的创新子表达式提取过程。此外，通过该技术派生的说明性单时钟硬件编码器已集成到1 GHz的90纳米和45纳米技术中，分别占用125 KG和107 KGate，实现了高达1.62 Tbps的吞吐速率。在本文中确定。在此介绍针对特定代码的创新子表达式提取过程。此外，通过该技术派生的说明性单时钟硬件编码器已集成到1 GHz的90纳米和45纳米技术中，分别占用125 KG和107 KGate，实现了高达1.62 Tbps的吞吐速率。