Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance degradation, profit reduction, and reputation risk for the manufacturer. Therefore, developing effective countermeasures against such malpractices is becoming severely crucial. Physical unclonable function (PUF)-based authentication methods have the potential to mitigate these challenges. However, PUF-based solutions are restrained by several factors, such as additional design efforts and significant area/power overhead, struggle to maintain and update challenge–response pairs (CRPs) database, and the vulnerability to machine learning (ML) attacks. In this article, we address these challenges by developing a novel database-free and enrolment-free hardware authentication approaches, i.e., a digital watermark metric for ICs. To enable efficient database-free hardware integrity verification without enrolment, first, we transform the intrinsic variations in circuit parameters, e.g., boundary scan chain (BSC) path delays in the joint test action group (JTAG) chain into robust digital signatures. Then, we perform statistical analysis on a small pilot unit of authentic chips to create a robust watermark for a complete batch of chips, which jointly captures the characteristics of the physical layout, the manufacturing process, and the foundry. The increasing complexity in the current state-of-the-art designs makes it extremely hard for an adversary to perfectly clone such statistical characterization of circuit parameters using counterfeit or compromised hardware. Besides, the proposed approach requires no additional design or hardware overhead in IC design since it utilizes an embedded structure, which inherently exists within the chips. It also obviates the design house from characterizing each manufactured chip instance, reducing overall testing cost. A path-delay measurement method at a high resolution based on clock phase sweep is introduced to measure the delay values effectively. The proposed intrinsic identifier-based authentication approach is validated by performing emulation on FPGAs and also by conducting physical measurements on custom-made printed circuit boards (PCBs). The reliability of the generated watermarks is evaluated with environmental temperature fluctuations and the aging effect.

中文翻译：

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微电子元器件的无数据库认证

由于供应链的日益复杂和分散的性质，伪造集成电路（IC）已成为半导体行业中的重要安全问题。这些假冒芯片可能会导致性能下降，利润减少以及制造商的声誉风险。因此，制定针对此类弊端的有效对策变得至关重要。基于物理不可克隆功能（PUF）的身份验证方法有可能缓解这些挑战。但是，基于PUF的解决方案受到多个因素的制约，例如，额外的设计工作和巨大的面积/功率开销，维护和更新挑战-响应对（CRP）数据库的努力以及机器学习（ML）攻击的脆弱性。在这篇文章中，我们通过开发一种新颖的无数据库和无注册的硬件认证方法（即用于IC的数字水印指标）来应对这些挑战。为了无需注册即可进行有效的无数据库硬件完整性验证，首先，我们将电路参数的固有变化（例如，联合测试行动组（JTAG）链中的边界扫描链（BSC）路径延迟）转换为可靠的数字签名。然后，我们对小型正宗芯片试点进行统计分析，以为完整批次的芯片创建可靠的水印，从而共同捕获物理布局，制造工艺和铸造厂的特征。当前最先进的设计中日益增加的复杂性使得对手极难使用伪造或受损的硬件完美地克隆这种电路参数的统计特征。此外，由于该方法利用了芯片内部固有的嵌入式结构，因此在IC设计中不需要额外的设计或硬件开销。这也避免了设计公司对每个制造的芯片实例进行特性描述，从而降低了总体测试成本。引入了一种基于时钟相位扫描的高分辨率路径延迟测量方法，可以有效地测量延迟值。通过在FPGA上执行仿真以及在定制印刷电路板（PCB）上进行物理测量，可以验证所提出的基于固有标识符的身份验证方法。