As emerging memories are utilized in processors as main memory, they must also coexist with CMOS memories; for instance SRAMs, are used to implement smaller, but faster associative memories. These hybrid designs exploit the advantages of both types of memories to achieve better performance. For some applications, the improvement in performance for on-chip associative memories is crucial for the overall computing system. For CMOS memories, soft errors are a major concern because they flip bits and can lead to data corruption and even a system failure. Error Detection and Correction Codes (EDCCs) are commonly used to protect memories against soft errors. In associative memories, an entry is formed by a tag and its associated data (or value). EDCCs are typically used to separately protect the tag and the data. This paper considers the protection of associative memories in which false negatives do not cause a failure. A Combined Tag and Data Parity (CTDP) protection scheme is proposed. This new approach utilizes a single parity bit per entry, so it reduces the number of parity bits needed to protect an entry as well as the memory size. The proposed scheme also reduces the complexity of read operations; it incurs the lowest circuit overhead for the protection circuitry in terms of area, delay and power consumption when compared to other schemes found in the technical literature. This makes the proposed scheme germane to associative memories used in hybrid designs that combine SRAMs and emerging memories. The extension of the proposed scheme to stronger codes is also discussed.

中文翻译：

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使用组合标签和数据奇偶校验 (CTDP) 保护关联存储器


由于新兴存储器在处理器中用作主存储器，因此它们也必须与CMOS存储器共存；例如 SRAM，用于实现更小但更快的关联存储器。这些混合设计利用两种类型存储器的优点来实现更好的性能。对于某些应用，片上关联存储器性能的提高对于整个计算系统至关重要。对于 CMOS 存储器，软错误是一个主要问题，因为它们会翻转位并可能导致数据损坏甚至系统故障。错误检测和纠正码 (EDCC) 通常用于保护存储器免受软错误的影响。在关联存储器中，条目由标签及其关联数据（或值）形成。 EDCC 通常用于单独保护标签和数据。本文考虑了对联想记忆的保护，其中假阴性不会导致失败。提出了一种组合标签和数据奇偶校验（CTDP）保护方案。这种新方法对每个条目使用一个奇偶校验位，因此减少了保护条目所需的奇偶校验位数量以及内存大小。所提出的方案还降低了读操作的复杂度；与技术文献中的其他方案相比，它在保护电路的面积、延迟和功耗方面带来的电路开销最低。这使得所提出的方案与结合 SRAM 和新兴存储器的混合设计中使用的关联存储器密切相关。还讨论了将所提出的方案扩展到更强的代码。