A bio-potential recorder working under 0.8 V supply voltage with a tunable low-pass filter is proposed in this paper. The prototype is implemented in TSMC 180 nm CMOS technology, featuring a power consumption of 2.27 $\mu$ W, while preserving a high tolerance of power-line interference (PLI) up to 600 m $V_{pp}$ , a common-mode rejection ratio (CMRR) of higher than 100 dB, a THD of −65.5 dB, and a noise density of 50 nV/ $\sqrt{Hz}$ by employing four new techniques, including 1) low noise chopper modulator, 2) feedback loop based common-mode cancellation loop (CMCL), 3) offset cancellation loop (OCL) with PMOS backgate control scheme, and 4) a very-lower transconductance (VLT) operational transconductance amplifier (OTA) using in the DC-servo-loop (DSL). The measured mid-band gain is 43.3 dB with a high-pass cut-off frequency of 1.2 Hz. The low-pass cut-off frequency can be configured from 650 Hz to 7.5 kHz. The measured input-referred integrated noise is 1.2 uVrms in the frequency band of 1-650 Hz and 4.1 uVrms in the 1 Hz–7.5 kHz frequency band, respectively, leading to a power efficiency factor (PEF) of 7.49 and 7.59.

中文翻译：

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0.8V电源下高抗电力线干扰的低噪声生物电位记录仪设计

本文提出了一种在 0.8 V 电源电压下工作的带有可调低通滤波器的生物电位记录仪。样机采用台积电 180 nm CMOS 工艺实现，功耗为 2.27$\mu$ W，同时保持对高达 600 m 的电力线干扰 (PLI) 的高耐受性 $V_{pp}$ ，共模抑制比 (CMRR) 高于 100 dB，THD 为 -65.5 dB，噪声密度为 50 nV/ $\sqrt{赫兹}$通过采用四种新技术，包括 1) 低噪声斩波调制器，2) 基于反馈回路的共模消除回路 (CMCL)，3) 具有 PMOS 背栅控制方案的偏移消除回路 (OCL)，以及 4) 极低的跨导(VLT) 运算跨导放大器 (OTA) 在直流伺服回路 (DSL) 中使用。测得的中频带增益为 43.3 dB，高通截止频率为 1.2 Hz。低通截止频率可配置为 650 Hz 至 7.5 kHz。测得的输入参考综合噪声在 1-650 Hz 频带内为 1.2 uVrms，在 1 Hz-7.5 kHz 频带内为 4.1 uVrms，导致功率效率因数 (PEF) 为 7.49 和 7.59。