Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time (Tret). For high device scalability and low program voltage (VP), lengths of the storage regions are determined by the sum of depletion widths of N- and P-storage regions. When doping concentrations of two storage regions are equal to each other at 1018 cm-3, 2-T TRAM exhibits the longest Tret of 100 ms and the lowest impact ionization of the device can suppress various reliability issues such as hot carrier injection and junction degradation. Although Tret of 2-T TRAM can be reduced from 100 ms to 1.5 ms due to decreased read voltage with operating temperature rising from 300 K to 360 K, Tret can be further improved to >10 s by applying standby voltage (Vstandby). The effective way to set minimum Vstandby is presented using the IA-VA characteristics with 1000-s fall time. Moreover, the optimal Vstandby is set to 0.60 V by considering disturbance in array operation. Consequently, the proposed design and operation guidelines can provide a pathway to realize nanoscale 2-T TRAM for capacitor-less 4F2 1T DRAM technology.

中文翻译：

---

两端晶闸管随机存取存储器的电气和数据保留特性


研究了基于纳米级交叉点垂直阵列的两端（2-T）晶闸管随机存取存储器（TRAM）的长数据保留时间（Tret）存储区域的长度和掺杂浓度。为了实现高器件可扩展性和低编程电压(VP)，存储区域的长度由N存储区域和P存储区域的耗尽宽度之和确定。当两个存储区域的掺杂浓度彼此相等为1018 cm-3时，2-T TRAM表现出最长100 ms的Tret，并且器件的最低碰撞电离可以抑制各种可靠性问题，例如热载流子注入和结退化。虽然随着工作温度从 300 K 上升到 360 K，由于读取电压降低，2-T TRAM 的 Tret 可以从 100 ms 减少到 1.5 ms，但通过施加待机电压 (Vstandby)，Tret 可以进一步提高到 >10 s。使用具有 1000 秒下降时间的 IA-VA 特性提出了设置最小 Vstandby 的有效方法。此外，考虑到阵列运行中的干扰，最佳Vstandby设置为0.60 V。因此，所提出的设计和操作指南可以为无电容器 4F2 1T DRAM 技术实现纳米级 2-T TRAM 提供途径。