A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm2 and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65° and a peak differential nonlinearity (DNL) of 0.25°.

中文翻译：

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12 位 0.5-2.4-GHz 0.65°-Peak-INL 寄生不敏感数相转换器

这封信中介绍了一种具有高线性度的 12 位 0.5-2.4GHz 寄生不敏感数相转换器 (DPC)。提出了一种改进的寄生不敏感电荷（PICB）相位插值器（PI），以避免寄生效应引起的线性退化。实现了一种具有分离时钟选择逻辑的新型 PI 单元，以解决电荷泄漏和过充电问题。DPC 采用 40-nm CMOS 技术设计和制造，芯片面积为 0.04 mm2，1.3-V 电源电压下的功耗为 18.3 mW。DPC 在 0.5 至 2.4 GHz 的频率范围内工作，表现出 0.65° 的峰值积分非线性 (INL) 和 0.25° 的峰值微分非线性 (DNL)。