The never-ending demands for battery-powered applications are driven by technological advances in the field of low power digital CMOS circuits. The voltage level shifters are crucial primitives for Systems-on-Chip (SoC) applications and systems operating with different voltage domains. In this article, three single supply energy-efficient low-power voltage level shifters are proposed that are suitable for input/output (I/O) and chip core interfaces in multi-core applications. The proposed level shifters are designed based on buffer and current mirror structures. The circuits are implemented in 180 nm technology and simulated using Cadence Spectre with two different supply voltages. The simulated results show better improvement in energy and average power of 2\(\times\), static power of 41.3\(\times\) and delay of 55.8\(\times\) @ 1.8 V than the existing level shifters. The voltage conversion range is from threshold voltage to I/O voltage level i.e, 580 mV to 3.3 V. The post-layout simulation confirms robustness of voltage level conversion of the proposed circuits. Due to a significant enhancement in delay, static power, energy and conversion range the proposed circuits are suitable for low-energy applications and low-power chip core-I/O interfacings.

低功耗数字CMOS电路领域的技术进步推动了对电池供电应用的永无止境的需求。电压电平转换器是片上系统（SoC）应用和在不同电压域下运行的系统的关键原语。在本文中，提出了三种适用于多核应用中的输入/输出（I / O）和芯片核接口的单电源节能低功率电压电平转换器。提出的电平转换器基于缓冲器和电流镜结构设计。电路以180 nm技术实现，并使用带有两个不同电源电压的Cadence Spectre进行仿真。仿真结果表明，能量和更好的平均功率提高了2 \（\ times \），静态功率提高了41.3\（\ times \）和比现有电平转换器高1.8V的55.8 \（\ times \）延迟。电压转换范围是从阈值电压到I / O电压电平，即580 mV到3.3V。布局后仿真证实了所提出电路的电压电平转换的鲁棒性。由于延迟，静态功率，能量和转换范围的显着提高，因此所提出的电路适用于低能耗应用和低功耗芯片内核I / O接口。