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Performance-Energy Trade-off in Modern CMPs
ACM Transactions on Architecture and Code Optimization ( IF 1.5 ) Pub Date : 2020-12-30 , DOI: 10.1145/3427092
Solomon Abera 1 , M. Balakrishnan 1 , Anshul Kumar 1
Affiliation  

Chip multiprocessors (CMPs) are ubiquitous in all computing systems ranging from high-end servers to mobile devices. In these systems, energy consumption is a critical design constraint as it constitutes the most significant operating cost for computing clouds. Analogous to this, longer battery life continues to be an essential user concern in mobile devices. To optimize on power consumption, modern processors are designed with Dynamic Voltage and Frequency Scaling (DVFS) support at the individual core as well as the uncore level. This allows fine-grained control of performance and energy. For an n core processor with m core and uncore frequency choices, the total DVFS configuration space is now m (n+1) (with the uncore accounting for the + 1). In addition to that, in CMPs, the performance-energy trade-off due to core/uncore frequency scaling concerning a single application cannot be determined independently as cores share critical resources like the last level cache (LLC) and the memory. Thus, unlike the uni-processor environment, the energy consumption of an application running on a CMP depends not only on its characteristics but also on those of its co-runners (applications running on other cores). The key objective of our work is to select a suitable core and uncore frequency that minimizes power consumption while limiting application performance degradation within certain pre-defined limits (can be termed as QoS requirements). The key contribution of our work is a learning-based model that is able to capture the interference due to shared cache, bus bandwidth, and memory bandwidth between applications running on multiple cores and predict near-optimal frequencies for core and uncore.

中文翻译:

现代 CMP 中的性能-能量权衡

芯片多处理器 (CMP) 在从高端服务器到移动设备的所有计算系统中无处不在。在这些系统中,能源消耗是一个关键的设计约束,因为它构成了计算云的最重要的运营成本。与此类似,更长的电池寿命仍然是移动设备中用户最关心的问题。为了优化功耗,现代处理器设计为在单个内核和非内核级别支持动态电压和频率缩放 (DVFS)。这允许对性能和能量进行细粒度控制。为n核心处理器核心和非核心频率选择,现在 DVFS 的总配置空间是 (n+1)(非核心占+ 1)。除此之外,在 CMP 中,由于内核共享关键资源,如最后一级缓存 (LLC) 和内存,因此无法独立确定单个应用程序的内核/非内核频率缩放导致的性能-能源权衡。因此,与单处理器环境不同,在 CMP 上运行的应用程序的能耗不仅取决于其特性,还取决于其共同运行者(在其他内核上运行的应用程序)的特性。我们工作的主要目标是选择合适的核心和非核心频率,以最大限度地降低功耗,同时将应用程序性能下降限制在某些预定义的限制内(可以称为 QoS 要求)。
更新日期:2020-12-30
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