ABSTRACT

Advancement in CMOS technology demands to revamp the design of basic functional units in digital systems. The binary addition is the basic operation in digital units like microprocessors, digital signal processors and data processing units in ASICs. Scaling down the technology no longer supports power density and energy-efficient digital architectures. The energy-efficient adder design demands the exploration of recurrence structures, existing algorithms, circuit design techniques, system constraints, energy and delay trade-offs. This paper presents the systematic design approach towards the design of an energy-efficient 64-bit parallel-prefix adder. A novel two-bit sum block reduces the power dissipation and the proposed recurrence algorithm further optimises the overall energy consumption. The 64-bit adder is implemented in static CMOS design and simulated in 45, 32, 22 and 16 nm technology nodes to validate the energy efficiency. In 45 nm technology, the proposed 64-bit parallel-prefix adder consumes 64.61% and 15.3% less energy compared to Brent–Kung and Ling adder respectively whereas in 16 nm technology, the proposed adder consumes 57.54% lesser energy than Brent–Kung adder and 14.28% lesser energy compared to the Ling adder.

摘要

CMOS 技术的进步要求改进数字系统中基本功能单元的设计。二进制加法是微处理器、数字信号处理器和 ASIC 中的数据处理单元等数字单元的基本操作。缩小技术不再支持功率密度和节能数字架构。节能加法器设计需要探索递归结构、现有算法、电路设计技术、系统约束、能量和延迟权衡。本文介绍了设计节能 64 位并行前缀加法器的系统设计方法。一种新颖的两位和块降低了功耗，并且所提出的递推算法进一步优化了整体能耗。64 位加法器在静态 CMOS 设计中实现，并在 45、32、22 和 16 nm 技术节点中进行仿真以验证能效。在 45 nm 技术中，与 Brent-Kung 和 Ling 加法器相比，建议的 64 位并行前缀加法器分别消耗 64.61% 和 15.3% 的能量，而在 16 nm 技术中，建议的加法器比 Brent-Kung 加法器消耗的能量少 57.54%与Ling加法器相比，能量减少了14.28%。