ABSTRACT

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively.

摘要

本文介绍了一种适用于宽输入范围的电压电源可扩展模拟电压比较器。使用基于数字门的方法来设计比较器，以扩展模拟设计中自动化的使用。因此，与传统的 CMOS 模拟电压比较器相比，所提出的比较器具有极大的成本效益，缩短了上市时间，可扩展到更新的技术，并且更不受工艺变化的影响。比较器采用半导体实验室 (SCL) 180 nm 数字 CMOS 技术设计，电源电压为 1.8 V。建议比较器的功耗约为 160 µW，总延迟和偏移电压分别为 1.63 ns 和 4.28 mV . 此外，还设计了 4 位和 5 位闪存 ADC 作为应用程序。DNL/INL的测量值为±0.4/±0.4LSB和0.42/±0。