As IoT is getting a thriving development, IC technology has stepped into the nano-meter era. For advanced 28 nm process and beyond, the device pitch becomes smaller. As a result, the coupling effect increases rapidly, degrading the performance of the critical design block, such as sense amplifiers in SRAM design. In addition, the process variation needs to be carefully addressed. In this paper we introduce an improvement over traditional latch type sense amplifier. The modification employs additional coupling effect in order to cancel out the device coupling observed in original design. The improved design shows a significant yield improvement based on the Monte-Carlo simulations under various operating conditions. The layout pattern modification is also presented, demonstrating an alternative sense amplifier implementation to address the coupling effect at negligible power and area overhead.

随着物联网的蓬勃发展，集成电路技术已经步入纳米时代。对于先进的 28 纳米及更高工艺，器件间距变得更小。结果，耦合效应迅速增加，降低了关键设计模块的性能，例如 SRAM 设计中的读出放大器。此外，需要仔细处理工艺变化。在本文中，我们介绍了对传统锁存型读出放大器的改进。该修改采用了额外的耦合效应，以抵消原始设计中观察到的设备耦合。基于各种操作条件下的 Monte-Carlo 模拟，改进后的设计显示出显着的良率提高。还介绍了布局模式修改，