Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 \(\upmu \)m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5\(\times \) higher performance and 2.4\(\times \) higher computational energy efficiency at a 1.6\(\times \) larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

为了在可靠的条件下工作，需要在坚固的技术节点中制造用于恶劣环境条件下（例如，高温或辐射暴露）的微控制器。但是，这些节点比尖端的半导体技术要大得多，并且速度较慢，从而大大降低了系统性能。为了实现较低的硅面积成本，低功耗和合理的性能，处理器体系结构组织本身是一个重要的影响设计点。诸如数据路径宽度，指令执行范式，代码密度，内存要求，高级控制流机制等参数可能会对设计约束产生很大影响。应用程序特征，例如可利用的数据并行性和所需的算术运算，为了有效地使用已实现的处理器资源，必须考虑这些因素。本文介绍了具有MIPS或ARM兼容指令集体系结构的五个不同体系结构的设计空间探索，以及传输触发的指令执行。使用0.18\（\ upmu \）米SOI CMOS技术用于高温和从通信领域的示例性情况的研究中，即，电力线载波通信的编码器，对性能和硬件效率建筑参数的影响进行了比较。对于这种应用，传输触发架构配置具有的8.5 \（\倍\）更高的性能和2.4 \（\倍\）在1.6更高的计算的能效\（\倍\）比为类较大的总的硅面积现成的ARM Cortex-M0嵌入式处理器，展示了针对不同体系结构的设计折衷范围。