Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips. Besides traditional interposers, which only provide passive elements and routing, active interposers are furthermore comprised of logic components. When implemented carefully using a dedicated electronic design automation (EDA) flow, an active interposer can significantly improve the design quality and flexibility for 2.5-D ICs. In this article, we present a complete EDA flow and design strategies targeting, such active interposer-based 2.5-D ICs. Our key contributions include the coanalysis of power, performance, signal and power integrity, and the related co-optimization of chiplets and the active interposer. Our benchmark is a 64-core RISC-V architecture, organized into multiple chiplets and interconnected by a system-level network-on-chip (NoC). For efficiency, we embed the NoC routers and integrated voltage regulators (IVRs) into the active interposer. Moreover, we integrate security monitors into the interposer-based NoC to protect the system and its shared memories against adversarial traffic. The simple yet powerful benefit of this implementation is to offer security by construction, as it is based on a clear physical separation between critical and trusted components (the system-level NoC) versus commodity components (the chiplets). We contrast our active, secured design to a passive, unsecured design baseline of the same RISC-V benchmark and find that the active design reduces the silicon area by 18.5%, power by 3.2%, and IR drop by 73.7%.

中文翻译：

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基于有源插入器的2.5D IC的设计流程以及具有安全NoC的RISC-V架构的研究

基于中介层的2.5-D集成电路（IC）使得芯片级重用硬知识产权（IP）也称为小芯片。这种系统级集成极大地缩短了大规模和异构芯片的设计周期。除了仅提供无源元件和布线的传统中介层之外，有源中介层还由逻辑组件组成。当使用专用的电子设计自动化（EDA）流程仔细实施时，有源插入器可以显着提高2.5D IC的设计质量和灵活性。在本文中，我们介绍了针对这类有源，基于中介层的2.5D IC的完整EDA流程和设计策略。我们的主要贡献包括功率，性能，信号和功率完整性的协分析，以及相关的小芯片和有源中介层的优化。我们的基准测试是64核RISC-V架构，被组织为多个小芯片并通过系统级片上网络（NoC）互连。为了提高效率，我们将NoC路由器和集成的稳压器（IVR）嵌入到有源插入器中。此外，我们将安全监控器集成到基于中介程序的NoC中，以保护系统及其共享内存免受敌对流量的侵害。此实现的简单而强大的好处是通过构造提供安全性，因为它基于关键和受信任组件（系统级NoC）与商品组件（小芯片）之间的明确物理隔离。我们将主动安全设计与被动安全设计进行对比，