This article focuses on the 3-D modeling methodology development of the wafer-to-wafer hybrid bonding (W2W-HB) annealing process. With its successful application in a 2-stack wafer-to-wafer bonding, the Cu-to-Cu bonding area is derived and compared for various design and process conditions, such as dishing value, annealing temperature, and dwell duration, through-silicon via (TSV) depth, and TSV/Cu pad pitch. Cu protrusion during the annealing process induces peeling stresses on both Cu and dielectric bonding interfaces. The resulting debonding risk for both Cu and dielectric bonding is assessed by comparing the peak interfacial peeling stresses for various scenarios. The impact of wafer designs with or without TSV has also been studied. The key advantage of this numerical study is to help establish design and process guidelines to shorten the W2W-HB process development cycle and achieve robust bonding integrity. The outcome of this work has been successfully implemented in the actual process.

中文翻译：

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通过先进的有限元建模为3D IC封装开发晶片对晶片的混合键合

本文重点介绍了晶圆间混合键合（W2W-HB）退火工艺的3-D建模方法开发。凭借其成功的2叠晶圆对晶圆键合技术，得出了Cu-Cu键合面积并针对各种设计和工艺条件进行了比较，例如凹陷值，退火温度和保压时间，直通硅（TSV）深度和TSV / Cu焊盘间距。退火过程中的铜突起会在铜和介电键合界面上引起剥离应力。通过比较各种情况下的峰值界面剥离应力，可以评估铜和介电键合产生的脱胶风险。还研究了带有或不带有TSV的晶圆设计的影响。这项数值研究的关键优势在于帮助建立设计和工艺准则，以缩短W2W-HB工艺开发周期并实现牢固的键合完整性。这项工作的成果已在实际过程中成功实施。