Autonomous microrobots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path-planning processor for 2-D/3-D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly exploring random tree (RRT) algorithm to ensure efficient planning on maps that have higher dimensions and a higher resolution. Dual-tree planning, branch extension, and parallel expansion are adopted in order to reduce both computational complexity and memory requirements. A prune-and-reuse strategy is also adopted so as to quickly respond to dynamic scenarios. An array of processing engines (PEs) is deployed in order to enable parallel expansion. The number of PEs is minimized through latency analysis. Low-complexity implementation for the PE is proposed while maintaining a high performance. Fabricated in a 40-nm CMOS technology, the chip integrates 2M logic gates in an area of 3.65 mm². The processor supports path-planning tasks for both 2-D and 3-D maps, with latencies of less than 1 and 10 ms, respectively. For a 2-D map that has 100 $\mathbf {\times }$ 100 grids, the proposed processor dissipates 1.5 $\boldsymbol{\mu }$ /task at a clock frequency of 200 MHz from a 0.9-V supply. Compared with the state-of-the-art designs, the proposed path-planning processor achieves a 1467 $\times $ shorter processing latency based on an energy dissipation that is 2133 $\times $ lower, despite the capability for larger maps.

中文翻译：

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用于微型机器人 2-D/3-D 自主导航的 1.5-μJ/任务路径规划处理器

自主微型机器人已被用于广泛的应用中。节能、实时的导航路径规划是必不可少的。这项工作提出了一种用于 2-D/3-D 自主导航的路径规划处理器。通过算法架构优化将能量和延迟降至最低。处理器利用快速探索随机树 (RRT) 算法来确保在具有更高维度和更高分辨率的地图上进行有效规划。采用双树规划、分支扩展和并行扩展，以降低计算复杂度和内存需求。还采用了剪枝重用策略，以快速响应动态场景。部署了一系列处理引擎 (PE) 以实现并行扩展。通过延迟分析最大限度地减少 PE 的数量。提出了 PE 的低复杂度实现，同时保持高性能。该芯片采用 40 纳米 CMOS 技术制造，在 3.65 毫米的面积内集成了 200 万个逻辑门² . 该处理器支持 2-D 和 3-D 地图的路径规划任务，延迟分别小于 1 和 10 毫秒。对于具有 100 $\mathbf {\times }$ 100 个网格，建议的处理器耗散 1.5 $\boldsymbol{\mu }$ /task 时钟频率为 200 MHz，来自 0.9 V 电源。与最先进的设计相比，所提出的路径规划处理器实现了 1467 $\times $ 基于能量耗散 2133 的更短处理延迟 $\times $ 较低，尽管有更大地图的能力。