A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.

中文翻译：

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EUV 中的 5nm 135Mb SRAM 和高迁移率通道 FinFET 技术，具有用于高密度和低 VMIN 应用的金属耦合和电荷共享写入辅助电路方案

一个 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T 高密度 SRAM 位单元，带有写辅助电路，通过使用具有 EUV 和高的 5-nm HK-金属栅极 FinFET 成功实现-移动通道（HMC）技术。本文提出了金属电容耦合负位线 (NBL) 和电荷共享低单元 VDD (CS-LCV) 写辅助技术，以降低 SRAM 的最小电源电压。还实施了飞位线 (FBL) 架构，以将高密度 SRAM 宏位密度提高 5%。硅数据显示，NBL 和 LCV 写辅助技术都可以在第 95 个百分位将整体 SRAM 最小电源电压性能提高 300 mV 以上。