Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 105 times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 ° C).

中文翻译：

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具有数据总线窗口扩展技术和协同片上 ECC 方案的 16 GB 640 GB/s HBM2E DRAM

介绍了用于增强 3-D 堆叠高带宽内存 2 扩展 (HBM2E) 的性能和可靠性的电路和设计技术。实施数据总线窗口扩展技术以应对从数据路径架构、硅通孔 (TSV) 放置和 TSV-PHY 对齐等范围内减少的时钟周期时间。阵列中间和芯片边缘的电源 TSV 放置以及用于电源网格的专用顶部金属将电源 IR 压降提高了 62%。具有自清洗功能的片上 ECC (OD-ECC) 方案被设计为与系统 ECC 正交。使用建议的 OD-ECC 和清理方案，不可纠正的误码率 (UBER) 提高了 105 倍。内存内置自检 (MBIST) 模块支持以并行方式进行低频单元和内核测试，以及所有通道全速运行，交流参数可调。建议的并行位 MBIST 将测试时间减少了 66%。采用第二代 10-nm 级 DRAM 工艺制造的 16-GB HBM2E 可实现高达 640 GB/s（5 Gb/s/pin）的带宽，并在高温（例如 105 ℃）。