A 128-Gb 1-bit/cell 3-D flash memory chip has been developed with 96-word-line-layer technology. A novel chip floorplan architecture with less time constants of wordline and bitline realizes fast read access time. A newly introduced program sequence achieves for higher reliability with less read-retry even after write/erase cycles. External VPP supply (12 V), current mode reference distribution, and auto temperature code refresh are also adopted to boost the performance of the chip. A new duty cycle corrector succeeds in obtaining wider unit interval of the DQS. Consequently, the proposed chip has a read access latency of 4 μs4~\mu \text{s} and a program time of 75 μs\mu \text{s} , which is 12–13 and 4–5 times faster than conventional 3-D flash memory with the same technology [Maejima et al., (2018)]. The random read latency (tRRL) is estimated to be less than 50 μs\mu \text{s} , which enables in the reduction of total read access time of solid state drive (SSD) system.

中文翻译：

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128Gb 1 位/单元 96 字行层 3D 闪存可改善随机读取延迟，tProg = 75 µs 且 tR = 4 µs


采用96字线层技术开发了128Gb 1位/单元3D闪存芯片。一种新颖的芯片布局架构，具有较少的字线和位线时间常数，实现快速读取访问时间。新引入的编程序列即使在写/擦除周期之后也能以更少的读重试实现更高的可靠性。还采用外部VPP电源（12V）、电流模式参考分配和自动温度代码刷新来提高芯片的性能。新的占空比校正器成功获得了更宽的 DQS 单位间隔。因此，所提出的芯片的读取访问延迟为 4 μs4~\mu \text{s} ，编程时间为 75 μs\mu \text{s} ，分别比传统的 3 快 12–13 和 4–5 倍。 -D 闪存采用相同的技术 [Maejima et al., (2018)]。随机读取延迟（tRRL）估计小于 50 μs\mu \text{s} ，这可以减少固态硬盘（SSD）系统的总读取访问时间。