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Enabling In-SRAM Pattern Processing with Low-Overhead Reporting Architecture
IEEE Computer Architecture Letters ( IF 1.4 ) Pub Date : 2020-07-01 , DOI: 10.1109/lca.2020.3042194
Elaheh Sadredini , Reza Rahimi , Kevin Skadron

The demand for accelerated pattern matching has motivated several recent in-memory accelerator architectures for automata processing, which is an efficient computation model for sophisticated pattern matching. Existing in-memory pattern matching architectures focus on accelerating the pattern matching kernel, but either fail to support a practical reporting solution or overlook the reporting stage. However, gathering and processing the reports can be the main bottleneck, especially for applications with high reporting frequency. Moreover, all the existing in-memory architectures work with a fixed processing rate (mostly 8 bits per cycle), and they do not adjust the input consumption rate based on the properties of the applications, which can lead to throughput and capacity loss. To address these issues, we present Sunder, an in-SRAM pattern matching architecture to processes a reconfigurable number of nibbles (4-bit symbols) in parallel, instead of fixed-rate processing, by adopting an algorithm/architecture methodology to perform hardware-award transformations. The key insight of our work is that transforming the commonly-used 8-bit processing to nibble-processing reduces required hardware resources (i.e., number of used memory rows) exponentially and achieves higher information density. This frees up space for storing reporting data in-place, which significantly eliminates host communication and reporting overhead. As a result, Sunder enables a low-overhead, energy-efficient, and high-performance in-memory pattern matching solution. Our results confirm that Sunder reporting architecture has zero performance overhead for 95% of the applications and incurs only 2% additional hardware overhead compared to the state-of-the-art solutions with no support for the reporting stage.

中文翻译:

使用低开销报告架构启用 In-SRAM 模式处理

对加速模式匹配的需求推动了最近几种用于自动机处理的内存加速器架构,这是一种用于复杂模式匹配的有效计算模型。现有的内存模式匹配架构专注于加速模式匹配内核,但要么无法支持实用的报告解决方案,要么忽略了报告阶段。但是,收集和处理报告可能是主要瓶颈,尤其是对于报告频率较高的应用程序。此外,所有现有的内存架构都以固定的处理速率(大多数为每周期 8 位)工作,并且它们不会根据应用程序的属性调整输入消耗速率,这会导致吞吐量和容量损失。为了解决这些问题,我们介绍了 Sunder,一种 SRAM 内模式匹配架构,通过采用算法/架构方法来执行硬件奖励转换,并行处理可重构数量的半字节(4 位符号),而不是固定速率处理。我们工作的关键见解是将常用的 8 位处理转换为半字节处理以指数方式减少所需的硬件资源(即使用的内存行数)并实现更高的信息密度。这为就地存储报告数据释放了空间,从而显着消除了主机通信和报告开销。因此,Sunder 实现了低开销、节能和高性能的内存模式匹配解决方案。
更新日期:2020-07-01
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