This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this brief, we address the challenges of process variations and discuss the circuits and methods used over the years to minimize this impact. We discuss the advantages of standard-cell library design and provide a more involved pruning method to improve performance and robustness. Finally, we discuss the developments of the usually ignored power delivery techniques for near/sub-threshold circuits. We motivate the use of voltage stacking as a new power delivery technique for near/sub-threshold. This brief provides the basic enablement approaches for designing a chip operating in the near/sub-threshold region based on our experience.

中文翻译：

---

近 20 年的近/亚阈值设计趋势和支持

本简报回顾了近 20 年来的近/亚阈值数字集成电路设计。大多数芯片都具有高度特性，可将电压缩小到接近/亚阈值，并且据报道进行了大量定制设计工作以实现可靠运行。在本简报中，我们解决了工艺变化带来的挑战，并讨论了多年来为最大限度地减少这种影响而使用的电路和方法。我们讨论了标准单元库设计的优势，并提供了一种更复杂的修剪方法来提高性能和鲁棒性。最后，我们讨论了近/亚阈值电路通常被忽略的功率传输技术的发展。我们鼓励使用电压堆叠作为近/亚阈值的新功率传输技术。