Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.

中文翻译：

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非二进制 LDPC 码的最小集格子最小-最大解码器架构

与现有的二进制对应物相比，非二进制低密度奇偶校验 (NB-LDPC) 码提供了卓越的纠错能力。然而，NB-LDPC解码器存在两个主要缺点，它们需要大量的硬件资源，特别是在校验节点单元（CNU），以及解码过程中的高延迟。在这个简介中，提出了一种用于 NB-LDPC 解码器的新的最小集网格最小-最大 (MS-TMM) 算法，以降低 CNU 的复杂度并提高解码吞吐量。基于所提出的 MS-TMM 算法的解码器架构是使用 90-nm CMOS 技术在 Galois 域 GF(32) 上为 (837, 726) NB-LDPC 码实现的。实施结果表明，与最先进的工作相比，所提出的架构大大降低了硬件复杂性和最高效率。