The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.

中文翻译：

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具有非时钟决策反馈均衡器的 112 Gb/s PAM-4 RX 前端

本简介中研究了用于高速 PAM-4 信号的非时钟 DFE (UC-DFE) 架构的实现。代替时钟限幅器和触发器，数据决策和反馈延迟控制由饱和模拟延迟链执行。因此，以前用于 NRZ 信号的 UC-DFE 节省了功耗和硅面积，同时简单的实现允许以高数据速率运行。包含线性均衡器和建议的 2-tap UC-DFE 方案的接收器前端采用 7 nm FinFET 技术设计。从布局后模拟中，接收器以 112 Gb/s 的速度在 18 dB 损耗信道后以 0.47 pJ/bit 的功率效率恢复 PAM-4 信号。接收器还以比特率一半的 NRZ 信号工作，均衡 24 dB 信道损耗，功率效率为 0.70 pJ/比特。