The reverse bias current of the tunneling field-effect transistor (TFET) could cause serious damage to static random-access memory (SRAM) circuit performance. To address this issue, a novel reverse bias current eliminated, read-separated, and write-enhanced TFET 12T SRAM bitcell is proposed for ultra-low power applications in this brief. It can prevent reverse bias currents, increase the hold/read static noise margin (H/RSNM) and dramatically decrease the static power consumption. The static power consumption of the proposed bitcell is reduced by four orders of magnitude compared with that of the 7T bitcell, demonstrating its great potential for ultra-low power applications. At a supply voltage of 0.6 V, the H/RSNM of the proposed bitcell is 25% larger than that of the 7T bitcell. It also includes a write assist circuit, thus increasing its write static noise margin (WSNM) and considerably decreasing its write power consumption. The WSNM of the proposed bitcell is more than twice that of the 7T bitcell, and is 60% larger than that of the combinational access bitcell. In addition, the write power consumption of the proposed bitcell is reduced by 95% compared with that of the combinational access bitcell at a supply voltage of 0.6 V. In terms of layout, the area of the proposed 12T bitcell is 92% larger than that of the 7T bitcell, but is 6% smaller than the area of the combinational access bitcell.

中文翻译：

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消除反向偏置电流、读取分离和写入增强的隧道 FET SRAM

隧道场效应晶体管 (TFET) 的反向偏置电流会对静态随机存取存储器 (SRAM) 电路性能造成严重损害。为了解决这个问题，本文提出了一种新型的消除反向偏置电流、读取分离和写入增强的 TFET 12T SRAM 位单元，用于超低功耗应用。它可以防止反向偏置电流，增加保持/读取静态噪声容限 (H/RSNM) 并显着降低静态功耗。与7T位单元相比，所提出的位单元的静态功耗降低了四个数量级，显示了其在超低功耗应用中的巨大潜力。在 0.6 V 的电源电压下，所提议的位单元的 H/RSNM 比 7T 位单元的 H/RSNM 大 25%。它还包括一个写辅助电路，从而增加其写入静态噪声容限 (WSNM) 并显着降低其写入功耗。所提出的位单元的WSNM是7T位单元的两倍以上，并且比组合存取位单元的WSNM大60%。此外，在0.6 V的电源电压下，与组合存取位单元相比，所提出的位单元的写入功耗降低了95%。在布局方面，所提出的12T位单元的面积比后者大92% 7T 位单元的面积，但比组合存取位单元的面积小 6%。