Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.

中文翻译：

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使用Vedic Nikhilam算法的快速有符号乘法器

Vedic算法有利于在高速计算和硬件设计中的应用。本研究提出了一种基于吠陀Nikhilam算法的快速有符号二进制乘法结构。作者探索了Nikhilam佛经，将无符号十进制数转换为有符号十进制和二进制操作数。拟议的乘法器通过将大操作数乘法转换为小操作数乘法以及加法运算，可以显着提高速度。拟议的设计是使用Xilinx ISE 14.4软件进行综合的，并使用不同的现场可编程门阵列器件来实现。拟议设计的效率取决于组合延迟，面积和功率。此外，新的乘法器体系结构比以前的设计实现了速度改进。