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Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems
Microelectronics Journal ( IF 1.9 ) Pub Date : 2020-12-18 , DOI: 10.1016/j.mejo.2020.104962
Zahra Zareei , Mehdi Bagherizadeh , MohammadHossein Shafiabadi , Yavar Safaei Mehrabani

In this paper, we present two novel approximate Full Adder cells with capacitive threshold logic (CTL) using carbon nanotube field-effect transistor (CNFET) technology. To investigate the efficiency of the proposed cells, extensive simulations are carried out at both application and transistor levels. At the application level, by using the MATLAB tool, the proposed cells are applied to the motion detector algorithm as one of the practical image processing applications. Peak signal-to-noise ratio (PSNR) is considered as a legitimate application-level evaluating factor. In addition, by using the HSPICE tool, the hardware level parameters such as average power consumption, delay, and power-delay product (PDP) are estimated. Then, a compromise between the application and hardware-level metrics is considered. Noise analysis is also accomplished by taking noise immunity curve (NIC) and average noise threshold energy (ANTE) into account. Furthermore, Monte Carlo transient analysis is exploited to study the robustness of the introduced cells against diameter deviations of the carbon nanotubes (CNTs). Simulation results indicate the supremacy of the proposed cells compared to others.



中文翻译:

利用CNFET技术设计适用于运动检测器系统的高效近似1位全加器单元

在本文中,我们使用碳纳米管场效应晶体管(CNFET)技术提出了两个具有电容性阈值逻辑(CTL)的新型近似全加器单元。为了研究所提出单元的效率,在应用和晶体管级都进行了广泛的仿真。在应用程序级别,通过使用MATLAB工具,将所提出的单元应用于运动检测器算法,作为实际的图像处理应用程序之一。峰值信噪比(PSNR)被视为合法的应用程序级评估因素。另外,通过使用HSPICE工具,可以估算出硬件级别参数,例如平均功耗,延迟和功率延迟乘积(PDP)。然后,考虑在应用程序和硬件级别指标之间进行折衷。噪声分析也可以通过考虑噪声抗扰度曲线(NIC)和平均噪声阈值能量(ANTE)来完成。此外,利用蒙特卡洛瞬态分析来研究引入的电池对碳纳米管(CNT)直径偏差的鲁棒性。仿真结果表明,与其他电池相比,拟议电池具有至高无上的地位。

更新日期:2020-12-23
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