Network-on-Chip (NoC) has emerged as a cost-effective on-chip interconnects solution for Tiled Chip Multi Processors (TCMP) where many computational cores occupy a single chip. The performance of NoC network can be greatly enhanced by incorporating 3D IC technology formed by stacking several active NoC layers using Through Silicon Via (TSV) vertical interconnections. 3D NoC routers improve network throughput and have minimal latency at the cost of increased router area and power dissipation. Performance degradation can occur in 3D structures due to unequal traffic distribution across the chip leading to larger power density and larger on-chip temperature that affect system reliability. In this paper, we come up with an interleaved vertical edge routing design approach in 3D NoC that employs asymmetrical routing algorithm and uses a unique flit prioritization unit for improving performance of bufferless mesh NoC. Experimental results indicate that our proposed router has better network performance with minimal hardware overhead when compared with conventional bufferless networks, engaging same number of routers.

片上网络（NoC）已经成为一种平价的片上互连解决方案，用于平铺式多芯片（TCMP），其中许多计算内核占用一个芯片。通过结合3D IC技术，可以大大提高NoC网络的性能，该技术是通过使用硅通孔（TSV）垂直互连堆叠几个有源NoC层而形成的。3D NoC路由器提高了网络吞吐量，并以增加的路由器面积和功耗为代价，具有最小的延迟。由于3D结构在芯片上的流量分配不均，可能导致性能下降，从而导致更大的功率密度和更大的片上温度，从而影响系统可靠性。在本文中，我们提出了一种3D NoC的交错式垂直边缘路由设计方法，该方法采用非对称路由算法，并使用独特的flit优先级划分单元来提高无缓冲网格NoC的性能。实验结果表明，与使用相同数量的路由器的传统无缓冲网络相比，我们提出的路由器具有更好的网络性能，并且硬件开销最少。