Abstract

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications.

中文翻译：

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基于FPGA的SRAM应用低位多位相邻纠错编解码器

摘要

大多数情况下，使用随机和相邻的纠错码来保护SRAM中存储的数据免受多重位翻转（MBU）的影响。由辐射引起的这些MBU是与静态随机存取存储器（SRAM）的可靠性有关的重要问题。结果，存储器的多个相邻位失真并且丢失了有价值的信息。为了减轻这些问题，在SRAM中最好使用多位相邻的纠错码。本文提出了单纠错-双误检测-双邻近纠错（SEC-DED-DAEC）码。所建议的SEC-DED-DAEC代码的性能在面积和延迟方面都得到了观察。与相关设计相比，建议代码的理论面积开销最多降低49.98％。此外，拟议的设计大约有28个。与现有设计相比，关键路径延迟减少了79％。与FPGA平台中的其他现有代码相比，在查找表（LUT）数量和延迟方面取得的最佳改进分别为22.69和29.98％。提议的代码可用于嵌入式SRAM应用中。