Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.

中文翻译：

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具有改进的软容错能力的可靠 SRAM 单元的片上自适应 VDD 缩放架构

负偏置温度不稳定性 (NBTI) 是主要的可靠性问题，它会影响许多参数，例如阈值电压、迁移率和漏电流。PMOS晶体管的阈值电压由于NBTI随着应力时间的增加而增加，这降低了电路性能。在本文中，我们提出了一种新颖的、可靠的、依赖于数据的低功耗 10T SRAM 单元，它高度稳定且没有半选择问题。我们使用 65nm CMOS 技术研究了所有电路模拟。与其他 SRAM 单元相比，建议的 10T 单元具有更高的临界电荷和更低的软错误率 (SER)。为了更好地评估，我们在读取操作中引入了位读取失败 (BRF)，并观察到与其他考虑的 SRAM 单元在 0.15V 电源下相比，所提议的 10T 单元的 BRF 显着降低。漏电功率， $0.1\times $ , $0.21\times $ ， 和 $3.13\times $ ，分别与 0.4V 电源下的传统 6T 电池相比。提议的细胞提供 $4\times $ , $1.15\times $ 和 $1.66\times $ 与 0.4V 电源电压下的 6T 单元相比，分别具有更高的读取、保持和写入裕度。仿真结果表明，10T 电池的 HSNM、WSNM 和 RSNM 分别降低了 0.31%、0.13% 和 0.08%，而 6T 电池在 10 年后分别降低了 3.21%、0.43% 和 8.62%。多年的压力时间。与传统阵列架构设计相比，我们还引入了片上自适应 VDD 缩放的可重构架构，以分别针对建议的 10T 单元在选定单元的读取和写入操作期间降低 97.04% 和 92.17% 的未选定单元的保持功率。