The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that considers the device electrostatics is necessary to predict and mitigate these soft errors in VLSI circuits. In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy-ion strike on OFF state NMOS. The output voltage perturbations due to ion strike in the CMOS inverter and the SET pulse width model are derived from the bias-dependent SET current model previously reported. The variations in the output voltage of the inverter and the pulse width obtained from the developed model for different Linear Energy Transfer (LET), supply bias, strike positions, device dimensions, and load capacitances are validated with TCAD mixed-mode simulations.

中文翻译：

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基于物理的 CMOS VLSI 电路单事件瞬态脉冲宽度模型

由于重离子撞击，MOSFET 中的单事件瞬态会在低于 50 纳米的 CMOS VLSI 电路中引入软错误。这些瞬变很容易在高频 CMOS VLSI 电路中捕获和传播。捕获率主要取决于单事件瞬态 (SET) 脉冲宽度和电路的时钟频率。通过考虑设备静电的基于物理的模型估计 SET 脉冲宽度对于预测和减轻 VLSI 电路中的这些软错误是必要的。在本文中，开发了一种基于物理的偏置相关模型，以确定双栅极 (DG) CMOS 反相器的 SET 脉冲宽度，其中重离子撞击关断状态 NMOS。由于 CMOS 反相器中的离子撞击和 SET 脉冲宽度模型，输出电压扰动源自先前报道的偏置相关 SET 电流模型。逆变器输出电压的变化以及从针对不同线性能量传输 (LET)、电源偏置、冲击位置、器件尺寸和负载电容的开发模型获得的脉冲宽度的变化，均通过 TCAD 混合模式仿真进行验证。