The ever-increasing need for computational power in embedded devices has led to the adoption heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising software technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This article demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59 percent, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference.

中文翻译：

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HePREM：基于 GPU 的异构 SoC 的可预测执行模型


嵌入式设备对计算能力的需求不断增长，导致采用将通用 CPU 与数据并行加速器相结合的异构 SoC。这些系统依赖于共享主内存 (DRAM)，这使得它们极易受到内存干扰。可预测执行模型 (PREM) 是一种很有前景的软件技术，可以应对这种影响。 PREM 通过将程序分为一系列内存和计算阶段，并通过强制执行平台级调度（一次只允许单个处理子系统执行内存阶段）来确保抗干扰的鲁棒性。本文首次演示了如何将 PREM 应用于异构 SoC，基于 CPU 和 GPU 之间内存隔离的同步技术以及将 GPU 内核转换为 PREM 兼容代码的编译器。对于与 CPU 共享 DRAM 带宽 50/50 的计算限制 GPU 工作负载，我们保证在性能损失仅为 59% 的情况下接近于零的时序可变性，这比我们在以下情况下看到的未修改程序的最坏情况小一到两个数量级：记忆干扰。