In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (L_Gs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for L_G = 13 nm corresponding to the (recent) state-of-the-art technology node for the “More Moore” options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (V_T), average subthreshold swing (SS_avg), OFF-state current (I_OFF), I_ON/I_OFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in V_T, I_OFF, I_ON/I_OFF, and SS_avg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of L_G (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SS_avg, a reduction of about 1 decade and 3 decades in I_OFF, and an improvement of nearly 1 decade and 2 decades in I_ON/I_OFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of I_OFF, I_ON/I_OFF and SS_avg with the lowest possible shifts in V_T (∼ 0%) and SS_avg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters.

在本文中，基于硅的非对称高架源漏隧道场效应晶体管 (AESD-TFET)，用于栅极长度 (L _G s)，即。70、45、32、22 和 13 nm，首次研究发现其在低于 400 mV 的低待机功耗 (LSTP) 数字操作中的适用性，随后发现其可靠性和稳定性正偏压温度不稳定性 (PBTI) 对 L _{G的不利影响}= 13 nm，对应于（最近的）最先进的技术节点，用于实现 LSTP 数字功能的“更多摩尔”选项。整个工作是在二维数值方法的帮助下执行的，通过模型校准分别针对高漏极 TFET (ED-TFET) 和高源源 TFET (ES-TFET) 的几个实验工作，然后通过三者之间的性能比较，在阈值电压（V _T）、平均亚阈值摆幅（SS _avg）、关闭状态电流（I _OFF）、I _ON /I _OFF比、关闭状态泄漏功率和漏极势垒降低 (DIBL)，然后测量 V _T、 I _OFF、 I _ON的变化/I _OFF , and SS _avg for different PBTI stress conditions for temperature ≥ 300 K. 对于 L _G的最佳值（即13 nm），DIBL 降低 56% 和 66%，降低 15.84% 和 45.74%在 SS _avg中， AESD-TFET 与 ES- 和 ED-TFET 器件相比，I _OFF减少了大约 1 个和 3个十年，I _ON /I _OFF提高了近 1 个和 2 个十年， 分别。_{在 I OFF}和 I _{ON的两个温度条件下（}即300 K 和 398 K），同样发现对 PBTI 效应具有最大稳定性/I _OFF和 SS _avg在 V _T (∼ 0%) 和 SS _avg (9%) 中的可能变化最小，此外还保持上述参数的最佳绝对值。