The advances in the new process technology characteristically come with a multitude of new design variables and hence a new set of challenges for the designers to understand the impact of circuit design. During the last decade, widespread deliberations have been specified to the usage of Gate Diffusion Input (GDI) networks in the design of digital core systems; however the logic design has been constructed using transistor-level. Till now there is no specific approach is available for synthesizing GDI circuit that incorporated the impact of signal arrangement and circuit technology. Creation of standard cell library for GDI technique becomes an utmost imperative. In this research work, a regimented synthesis algorithm have been proposed to minimize power and augment performance of the digital circuits through two approaches MUX based decomposition algorithm and Binary Decision Diagram (BDD). The primitive nodes are implemented by GDI logic and CMOS logic for level restoration circuit. This research work is targeted to design sub-micron GDI library which is suitable for the 180 ​nm and 90 ​nm 6-metal layer CMOS n-well process which is offered by MOSIS. The principal focus is to engender a comprehensive library including the core number of essential primitive cells, depicting the detailed layout and transistor-level schematic views of every cell in 180nm and 90 ​nm process, in order to use them as a completely synthesizable library. The signal connectivity models for GDI are presented using MUX and BDD approach. The synthesis of ISCAS Combinational bench mark circuit in CMOS, PTL and GDI technique is also examined in this work along with buffer inclusion procedure for GDI technique.

新工艺技术的进步通常伴随着许多新的设计变量，从而给设计人员理解电路设计的影响带来了新的挑战。在过去的十年中，已经在数字核心系统的设计中广泛考虑了门扩散输入（GDI）网络的使用。但是，逻辑设计是使用晶体管级构建的。到目前为止，尚无可用于综合考虑信号布置和电路技术影响的GDI电路的特定方法。创建用于GDI技术的标准单元库成为当务之急。在这项研究工作中，通过基于MUX的分解算法和二进制决策图（BDD）两种方法，提出了一种有条理的综合算法，以最小化功率并增强数字电路的性能。基本节点由GDI逻辑和CMOS逻辑实现电平恢复电路。这项研究工作旨在设计亚微米GDI库，该库适用于MOSIS提供的180 nm和90 nm 6金属层CMOS n阱工艺。主要重点是建立一个综合库，其中包括必不可少的基本单元的核心数量，描绘180nm和90nm工艺中每个单元的详细布局和晶体管级示意图，以便将它们用作完全可综合的库。使用MUX和BDD方法介绍了GDI的信号连接模型。