This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. Conventional ternary circuit designs use single V_DD power supply, which is not a power-efficient technique. In these designs, the intermediate ternary logic state (V_DD/2) is generated by allowing a steady-state current through two diode-connected transistors connected in series and the output is obtained from the junction of the two transistors. The proposed dual-V_DD HA design utilizes both the available ternary power supply voltages (V_DD & V_DD/2) and prevents direct path between the power supplies and ground, in all the three possible ternary logic output states, resulting in a significant reduction in power consumption.

While Carbon Nanotube FETs (CNFETs) is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed dual-V_DD ternary dynamic HA design has been implemented with both CNFET and 45 nm CMOS devices. The proposed CNFET HA has an average delay of merely 8.4 ps, which is lower than the delays experienced in conventional designs (16.5–60.5 ps). The overall decrease in Power Delay Product (PDP) is 72–98% in the proposed CNFET HA, with respect to the other designs reported in the literature.

本文提出了一种超低功耗三元动态半加法器（HA）设计，该设计仅消耗83 nW的功率，与文献中报道的其他设计相比，其功耗降低了66–90％。常规三元电路设计使用单个V _DD电源，这不是一种节能技术。在这些设计中，通过允许稳态电流通过两个串联的二极管连接的晶体管来产生中间三元逻辑状态（V _DD / 2），并从两个晶体管的结点获得输出。拟议的双V _DD HA设计同时利用了可用的三态电源电压（V _DD和V_DD / 2），并在所有三种可能的三态逻辑输出状态下防止电源与地之间的直接路径，从而大大降低了功耗。

尽管碳纳米管FET（CNFET）在低功耗VLSI应用中受到世界各地许多研究人员的青睐，但由于拥有先进的CMOS制造单元，CMOS技术仍在业界广泛使用。因此，建议的双V _DD三元动态HA设计已经在CNFET和45 nm CMOS器件中实现。拟议的CNFET HA的平均延迟仅为8.4 ps，低于传统设计中的延迟（16.5–60.5 ps）。与文献中报道的其他设计相比，拟议的CNFET HA中的功率延迟积（PDP）总体降低了72–98％。