Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si_0.93Ge_0.07 spacers on both sides of P-doped Si layers, and substituting SiH₄ by SiH₂Cl₂ (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si_0.93Ge_0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure.

垂直栅绕型场效应晶体管（vGAAFET）被认为是替代FinFET的潜在候选者，用于3nm技术节点以上的先进集成电路制造技术。通常生长和处理Si / SiGe / Si的多层（ML）以形成垂直晶体管。在这项工作中，已经研究了在Si / SiGe / Si中进行P掺入并垂直蚀刻这些ML，然后在横向选择性蚀刻SiGe形成vGAAFET的结构。几种策略提出的外延诸如氢气吹扫以耗尽P原子对Si表面的访问，和/或插入的Si或Si _0.93锗_0.07上P型掺杂硅层的两侧间隔物，而代的SiH ₄通过的SiH ₂ Cl ₂（DCS）。实验结果表明，向P掺杂的Si中添加7％的Ge也可以缓解偏析和自掺杂。该结构具有良好的晶格质量并且几乎没有应变松弛。还通过湿法和干法刻蚀讨论了P掺杂Si（或P掺杂Si _0.93 Ge _0.07）与SiGe之间的选择性刻蚀。还比较了不同蚀刻方法的性能和选择性。本文提供了有关如何应对垂直GAAFET结构中的外延和n型层蚀刻的挑战或困难的知识。