The Clock Constraint Specification Language (CCSL) is a clock-based specification language for real-time embedded systems. With logical clocks defined as first-class citizens, CCSL provides a natural way for describing clock constraints in synchronous systems — a classical model of concurrency for real-time embedded systems. In this paper, we propose a clock-based dynamic logic called CCSL Dynamic Logic (CDL) for the verification of CCSL specifications in synchronous systems. It extends the first-order dynamic logic with a synchronous execution mechanism in its program model and with CCSL primitives as terms in its logical formulae. We build a sound and relatively complete proof system for CDL to support the verification. Compared with previous approaches for verifying CCSL specifications, which are based on model checking and SMT checking techniques, our approach, which is based on theorem-proving, offers a unified verification framework in which both bounded and unbounded CCSL specifications can be verified. Technically, with the proof system of CDL, a complex CDL formula can be semi-automatically transformed into a set of quantifier-free, arithmetical first-order logic (QF-AFOL) formulae which can be checked by an SMT solver in an efficient way. As a case study, we analyze a simple synchronous system throughout the paper to illustrate how CDL works. We analyze and prove the soundness and completeness of the proof system for CDL. Currently, CDL is partially mechanized in Coq.

时钟约束规范语言（CCSL）是用于实时嵌入式系统的基于时钟的规范语言。通过将逻辑时钟定义为头等公民，CCSL提供了一种自然的方式来描述同步系统中的时钟约束-实时嵌入式系统并发性的经典模型。在本文中，我们提出了一种基于时钟的动态逻辑，称为CCSL动态逻辑（CDL）用于验证同步系统中的CCSL规范。它通过程序模型中的同步执行机制以及逻辑表达式中的CCSL原语扩展了一阶动态逻辑。我们为CDL建立了完善且相对完整的证明系统，以支持验证。与以前的基于模型检查和SMT检查技术的CCSL规范验证方法相比，我们的基于定理证明的方法提供了一个统一的验证框架，可以在其中验证有界和无界CCSL规范。从技术上讲，借助CDL的证明系统，可以将一个复杂的CDL公式半自动转换为一组无量词，可以由SMT求解器以有效方式检查的算术一阶逻辑（QF-AFOL）公式。作为案例研究，我们将在整篇论文中分析一个简单的同步系统，以说明CDL如何工作。我们分析并证明了CDL证明系统的健全性和完整性。当前，CDL在Coq中已部分机械化。