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Improving the Performance of Hybrid Caches Using Partitioned Victim Caching
ACM Transactions on Embedded Computing Systems ( IF 2.8 ) Pub Date : 2020-12-07 , DOI: 10.1145/3411368
Sukarn Agarwal 1 , Hemangee K. Kapoor 1
Affiliation  

Non-Volatile Memory technologies are coming as a viable option on account of the high density and low-leakage power over the conventional SRAM counterpart. However, the increased write latency reduces their chances as a substitute for SRAM. To attenuate this problem, a hybrid STT-RAM-SRAM architecture is proposed where with large STT-RAM ways, the small SRAM ways are incorporated for handling the write operations. However, the performance gain obtained from such an architecture is not as much as expected on account of the larger miss rate caused by smaller SRAM partition. This, in turn, may limit the amount of cache capacity. This article attempts to reduce the miss penalty and improve the average memory access time by retaining the victims evicted from the hybrid cache in a smaller, fully associative SRAM structure called the victim cache. The victim cache is accessed on a miss in the primary hybrid cache. Hits in the victim cache require an exchange of the block between the main hybrid cache and the victim cache. In such cases, to effectively place the required block in the appropriate region of the main hybrid cache, we propose an access-based block placement technique. Besides, to manage the runtime load and the uneven evictions of the SRAM partition, we also present a dynamic region-based victim cache partitioning method to hold the victims dedicated to each region. Experimental evaluation on a full system simulator shows significant improvement in the performance and execution time along with a reduction in the overall miss rate. The proposed policy also increases the endurance of Hybrid Cache Architectures (HCA) by reducing writes in the STT partition.

中文翻译:

使用分区受害者缓存提高混合缓存的性能

非易失性存储器技术正在成为一种可行的选择,因为它比传统的 SRAM 对应物具有高密度和低泄漏功率。然而,增加的写入延迟降低了它们作为 SRAM 替代品的机会。为了减轻这个问题,提出了一种混合 STT-RAM-SRAM 架构,其中使用大型 STT-RAM 通道,并结合小型 SRAM 通道来处理写入操作。然而,由于较小的 SRAM 分区会导致较大的未命中率,因此从这种架构中获得的性能增益并没有预期的那么大。反过来,这可能会限制缓存容量。本文试图通过将被从混合缓存中逐出的受害者保留在一个称为受害者缓存的更小、完全关联的 SRAM 结构中来减少未命中损失并提高平均内存访问时间。在主混合缓存中未命中时访问受害者缓存。受害缓存中的命中需要在主混合缓存和受害缓存之间交换块。在这种情况下,为了有效地将所需块放置在主混合缓存的适当区域中,我们提出了一种基于访问的块放置技术。此外,为了管理运行时负载和 SRAM 分区的不均匀驱逐,我们还提出了一种基于动态区域的受害者缓存分区方法,以将受害者专用于每个区域。对完整系统模拟器的实验评估表明,性能和执行时间显着提高,同时整体未命中率降低。提议的策略还通过减少 STT 分区中的写入来提高混合缓存架构 (HCA) 的耐用性。
更新日期:2020-12-07
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