Traditional literature on analog testing deals with the propagation of faults to the output ports of a circuit. Often the percentage of detected faults remains low because suitable stimuli cannot be found for propagating certain faults to the outputs. Existing technology supports monitoring internal nets of a circuit, thereby improving fault detection by observing their effect on internal nets. However, this approach is feasible only if the number of internal nets probed by the built-in test structure is limited. This paper presents a structured approach that identifies a small well-chosen subset of internal nets which, when probed, can increase the coverage of analog faults. Further, it describes a formal methodology to identify distinct sub-circuits in a given design, that could be independently probed for detection of faults. Thus, for a given fault universe, the complexity of simulations can be reduced significantly by simulating only the sub-circuits rather than the entire design. We utilize the speed of DC analysis, some common features of analog signals, and partitioning of the transistor netlist using a Channel Connected Graph to accomplish this outcome. We report significant improvement in fault coverage on several circuits including some Analog/Mixed-Signal benchmarks.

关于模拟测试的传统文献涉及将故障传播到电路的输出端口。通常，检测到的故障的百分比仍然很低，因为找不到合适的激励将某些故障传播到输出。现有技术支持监视电路的内部网络，从而通过观察它们对内部网络的影响来改进故障检测。但是，只有在内置测试结构探测到的内部网络数量有限的情况下，这种方法才可行。本文提出了一种结构化的方法，该方法可以识别内部网络的一小部分精心挑选的子集，当对其进行探测时，可以增加模拟故障的覆盖范围。此外，它描述了一种正式的方法论，可以识别给定设计中的不同子电路，可以对这些子电路进行独立探测以检测故障。从而，对于给定的故障范围，仅模拟子电路而不是整个设计，可以大大降低模拟的复杂性。我们利用DC分析的速度，模拟信号的一些常见功能以及使用通道连接图对晶体管网表进行分区来实现此结果。我们报告了包括模拟/混合信号基准在内的若干电路的故障覆盖率显着提高。