Chip-package interaction-caused mobility degradation in CMOS transistors is a critical degradation mechanism for microelectronic devices. An approach based on nondestructive indentation is applied to induce highly localized stress fields. Strain-sensitive ring oscillator circuits are integrated to monitor parametric deviations during mechanical loading. In this study, the indentation technique is used to investigate the impact of the chip layout and geometry of a flip chip-packaged test chip. Complementary FE simulation provides a better understanding of the relevant stress-strain fields and enables a comparison of the parametric circuit deviations within a dedicated stress tensor. The results demonstrate the capability to study the stress-strain distribution in microelectronic devices during external loading with indentation and to determine its impact on transistor degradation.

中文翻译：

---

用压痕研究芯片布局对应力引起的迁移率退化的影响

CMOS 晶体管中芯片-封装相互作用引起的迁移率下降是微电子器件的关键退化机制。一种基于非破坏性压痕的方法被应用于诱导高度局部化的应力场。集成了应变敏感环形振荡器电路以监控机械加载期间的参数偏差。在这项研究中，压痕技术用于研究倒装芯片封装测试芯片的芯片布局和几何形状的影响。互补 FE 模拟提供了对相关应力-应变场的更好理解，并能够比较专用应力张量内的参数电路偏差。