In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

在本文中，针对集成电路 (IC) 提出了一种电路级可靠的低泄漏设计方法。由于对电池供电的便携式系统的需求不断增加，低泄漏电路设计是超大规模集成 (VLSI) 电路设计人员最具挑战性的研究领域。随着深亚微米 (DSM) 领域中每个新技术节点的产生，漏电功率不断增加。大功率耗散会损害器件特性并影响电路的整体性能。针对低功耗操作和可靠性，对所提出的方法进行了广泛讨论和验证。使用 HSPICE 工具上的预测技术模型 (PTM) bulk CMOS BSIM4，对各种逻辑电路进行了仿真，并与 22 nm 技术节点上可用的泄漏最小化技术进行了比较。与传统的 CMOS 门相比，所提出的方法将 XOR2 和 XNOR2 门中的泄漏功率降低了 ≈81%。纳米级电路的可靠性受几个器件参数的影响。可靠性测试考虑了工艺、电压和温度 (PVT) 变化、老化和辐射效应。与传统电路相比，针对环形振荡器的功率延迟积 (PDP) 指标，所提出方法的可靠性提高了 77.45%。