Task migration plays an important role in load balancing and energy savings in data centers. It also challenges service providers to minimize service interruptions during task migration. FPGA computing requires checkpointing as an essential function for hardware task migration. However, the current methods of implementing such a function for FPGAs have a high cost in hardware resources and significant degradation in performance. To overcome these problems, in this paper we propose a system using checkpointing at the hardware description language (HDL) level for hardware task migration. First, we propose a hardware task migration scheme in which checkpointing procedures and context transfer can overlap to reduce the service downtime. Second, we present a new checkpointing architecture for FPGAs that flattens the structure of nested modules at the HDL level. Third, we propose a static analysis of the original HDL source code to reduce the cost of hardware. Fourth, we introduce a Python-based tool to generate the checkpointing architecture at the HDL level. We evaluated our checkpointing architecture and the migration scheme using four application benchmarks running on a heterogeneous FPGA cluster. Our evaluations showed that the migration downtime was minimized at only 1.251 ms in the S-Search benchmark. When compared with a tree-based checkpointing architecture, the proposed architecture with the static analysis can reduce the LUT overhead by up to 50%, on the average. The checkpointing hardware caused small degradation in the maximum clock frequency (1.66% on the average), and consumed small memory footprints. Other comparisons with the previous hardware task migration scheme highlight the advantages of our migration scheme.

任务迁移在数据中心的负载平衡和节能中起着重要作用。它还要求服务提供商在任务迁移期间最大程度地减少服务中断。FPGA计算需要检查点作为硬件任务迁移的基本功能。然而，当前用于FPGA实现这种功能的方法在硬件资源上具有很高的成本，并且在性能上有很大的降低。为了克服这些问题，本文提出了一种在硬件描述语言（HDL）级别上使用检查点进行硬件任务迁移的系统。首先，我们提出了一种硬件任务迁移方案，其中检查点过程和上下文传输可以重叠以减少服务停机时间。第二，我们为FPGA提供了一种新的检查点架构，该架构在HDL级别上展平了嵌套模块的结构。第三，我们建议对原始HDL源代码进行静态分析，以降低硬件成本。第四，我们引入了一个基于Python的工具来在HDL级别上生成检查点架构。我们使用在异构FPGA集群上运行的四个应用程序基准评估了检查点架构和迁移方案。我们的评估表明，在S-Search基准测试中，迁移停机时间仅在1.251 ms时被最小化。与基于树的检查点体系结构相比，所提出的具有静态分析的体系结构平均可将LUT开销降低多达50％。检查点硬件对最大时钟频率的影响很小（平均为1.66％），并占用少量内存。与以前的硬件任务迁移方案的其他比较突出了我们迁移方案的优势。