A four-channel, power-efficient, low-noise neural recording analog front-end (AFE) integrated circuit (IC) comprised of a low-noise amplifier (LNA), a programmable gain amplifier (PGA), and buffers is presented. The proposed AC-coupled capacitive-feedback LNA utilizes the inverter-stacking technique for the core operational transconductance amplifier which achieves four-time reduction in noise at minimal power consumption. The proposed PGA provides additional gain with tunable filtering function where the high-pass cut-off and low-pass cut-off frequencies can be controlled to acquire action potential and local field potential signals either simultaneously or separately. The overall AFE IC has a programmable gain range from 45 ​dB to 63 ​dB and achieves integrated input-referred noise of 3.16 μV_RMS within the 10 ​kHz bandwidth, leading to a noise efficiency factor of 2.04 and power efficiency factor of 4.16. The AFE IC is implemented using 180 ​nm CMOS process and consumes 2.82 ​μW per channel powered from the 1-V supply voltage.

提出了一种四通道，省电，低噪声的神经记录模拟前端（AFE）集成电路（IC），该集成电路由低噪声放大器（LNA），可编程增益放大器（PGA）和缓冲器组成。拟议的交流耦合电容反馈LNA将逆变器堆叠技术用于核心运算跨导放大器，从而以最小的功耗实现了四倍的噪声降低。拟议的PGA通过可调滤波功能提供了额外的增益，可以控制高通截止频率和低通截止频率，以同时或分别获取动作电位和局部场电位信号。整体AFE IC具有从45 dB到63分贝可编程增益范围并实现集成输入参考噪声3.16μV的_RMS在10 kHz带宽内，导致噪声效率系数为2.04，功率效率系数为4.16。AFE IC使用180纳米CMOS工艺实现，由1-V电源电压供电的每通道功耗为2.82μW。